Hardware Configuration and Definition (HCD) for z/OS

Schedule

Start End Duration Location Details

Course Details

Hardware Configuration and Definition (HCD) for z/OS

Course code: ES96G

Duration: 4 Days


Prerequisite:

You should have: 

•    A basic knowledge of z/OS and I/O configuration
•    This knowledge can be developed on the job, or by taking Fundamental System Skills in z/OS (ES10A).

Course Description:

Learn to work with the Hardware Configuration Definition (HCD) function for z/OS, and to plan and initiate dynamic reconfiguration of your zSeries hardware environment. Learn to use the HCD dialogs of z/OS to create an Input/Output (I/O) configuration and dynamically alter the I/O configuration. Learn about the creation of an I/O Configuration Dataset (IOCDS) and various reports that HCD can build. Use a z/OS system to reinforce lecture topics and to practice working with the HCD dialogs. Hands-on lab projects may be done in teams depending on the number of attendees and location.

Course Objectives:

After taking this course, you should be able to:

•    Describe new zSeries processor technology
•    Code new zSeries processors (z9 to z196)
•    Code FICON channels and FICON CTCs
•    Code Coupling Facilities (CF) and CF links
•    Code cascaded FICON Directors
•    Create an IODF work file on a z processor from scratch
•    Use CHPID mapping tool to create a validated work IODF
•    Use work IODF and create a production IODF
•    Perform Dynamic I/O changes on a real z/OS system
•    Build a LOADxx parmlib member for initial program load (IPL)
•    View configuration graphically
•    Create appropriate configuration reports    

Intended Audience:

•    This course is for people who are responsible for maintaining the I/O configuration contained in the input/output data files (IODFs) and input/output configuration data sets (IOCDs) at their z/OS installation.

Course Outlines:

•    Day 1
o    Welcome
o    Unit 1: HCD introduction
o    Unit 2: IOCP and MVSCP macro review
o    Unit 3: HCD dialog
o    Unit 4: LPAR and logical control unit concepts
o    Unit 5: OSAs, OSA/ICC and HiperSockets
o    Unit 6: Review of zSeries hardware
o    Exercise 1: Overview of lab environment
o    Exercise 2: HCD familiarity

•    Day 2
o    Unit 7: zSeries I/O architecture: Logical channel subsystems
o    Unit 8: Advanced DASD concepts: EAV/PAV and multiple subchannel sets
o    Unit 9: FICON, FICON CTCs, and FICON directors
o    Exercise 3: Coding a zSeries 2817
o    Exercise 4: Adding FICON directors to your configuration (optional)
o    Exercise 5: Incremental migration from IOCP deck (optional)

•    Day 3
o    Unit 10: HCD implementation and migration
o    Unit 11: IPL and LOADxx member
o    Unit 12: Dynamic I/O reconfiguration
o    Unit 13: z196 HCD and using CMT
o    Exercise 6: Building a LOADxx member
o    Exercise 7: Perform dynamic I/O

•    Day 4
o    Unit 14: FICON CTCs for sysplex
o    Unit 15: HCD and Parallel Sysplex
o    Exercise 8: Coding a 2817 using the CMT
o    Exercise 9: Coding CF coupling links
o    Exercise 10: Coding sysplex FICON CTCs